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SRAM
Austin Semiconductor, Inc. 128K x 8 SRAM
WITH DUAL CHIP ENABLE ULTRA LOW POWER
AVAILABLE AS MILITARY SPECIFICATIONS
*MIL-STD-883, para. 1.2.2 compliant
MT5C1008(LL) Ultra Low Power
PIN ASSIGNMENT (Top View)
32-Pin DIP (C)
NC A16 A14 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 26 27 25 24 23 22 21 20 19 18 17
VCC A15 CE2 WE\ A13 A8 A9 A11 OE\ A10 CE1\ I/O7 I/O6 I/O5 I/O4 I/O3
FEATURES
* * * * * * * * High Speed: 30 ns Low active power: 715 mW worst case Low CMOS standby power: 3.3 mW worst case 2.0V data retention, Ultra Low 0.3mW worst case power dissipation Battery backup applications Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE1\, CE2, and OE\ options
A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
OPTIONS
* Timing 30ns access * Package(s) Ceramic DIP (400 mil) * Temperature Military (-55C to +125C)
MARKING
-30
GENERAL DESCRIPTION
C No. 111 The MT5C1008 SRAM is a high-performance CMOS static RAM organized as 131, 072 words by 8 bits, offering low active power and ultra low standby and data retention current levels. Easy memory expansion is provided by an active LOW Chip Enable (CE1\), an active HIGH Chip Enable (CE2), and active Low Output Enable (OE\), and three-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1\) and Write Enable (WE\) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable One (CE1\) and Output Enable (OE\) LOW while forcing Write Enable (WE\) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1\) HIGH or CE2 LOW), the outputs are disabled (OE\ HIGH), or during a write operation (CE1\ LOW, CE2 HIGH, and WE\ LOW).
MIL
* Options 2V data retention/very low power
LL
For more products and information please visit our web site at www.austinsemiconductor.com
MT5C1008(LL) Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
Austin Semiconductor, Inc.
MT5C1008(LL) Ultra Low Power
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
MODE Power-Down Power-Down Read Write Selected, Outputs Disabled OE\ X X L X H CE1\ H X L L L CE2 X L H H H WE\ X X H L H I/O0 - I/O7 High Z High Z Data Out Data In High Z POWER Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
MT5C1008(LL) Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage Range on Vcc to Relative GND ..-0.5V to +7.0V Storage Temperature .............................................-65C to +150C Ambient Temperature with Power Applied........-55C to +125C DC Voltage Applied to Outputs in High Z State1.................................................-0.5V to Vcc + 0.5V DC Input Voltage1.............................................-0.5V to Vcc + 0.5V
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MT5C1008(LL) Ultra Low Power
*Stresses at or greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods will affect reliability. Refer to page 17 of this data sheet for a technical note on this subject. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (-55oC < TC < 125oC; VCC = 5.0V +10%)
-30 PARAMETER Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Vcc Operating Supply Current Automatic CE PowerDown Current - TTL Inputs Automatic CE PowerDown Current - CMOS Inputs GND < VI < Vcc GND < VI < Vcc, Output Disabled Vcc = MAX, IOUT = 0 mA f = f = 1/tRC MAX Vcc, CE1\ > VIH or CE2 < VIL, VIN > VIH or VIN < VIL, f = fMAX MAX Vcc, CE1\ > Vcc - 0.3V, or CE2 < 0.3V, VIN > Vcc - 0.3V, or VIN < 0.3V, f = 0 ISB1 4 mA CONDITIONS Vcc = MIN, IOH = -4.0 mA Vcc = MIN, IOL = 8.0 mA SYM VOH VOL VIH VIL IIX IOZ ICC 2.2 -0.3 -10 -10 MIN 2.4 0.4 VCC+0.3 0.8 +10 +10 MAX UNITS V V V V A A 1 NOTES
130
mA
ISB2
0.6
mA
NOTES: 1. VIL(MIN) = -2.0V for pulse durations of less than 20ns.
MT5C1008(LL) Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
Austin Semiconductor, Inc.
CAPACITANCE1
PARAMETER Input Capacitance (A0 - A16) Input Capacitance (CE\, WE\, OE\) Output Capacitance
NOTES: 1. Tested initially and after any design or process changes that may effect these parameters.
MT5C1008(LL) Ultra Low Power
SYM CIN MAX 8 10 12 UNITS pF pF pF
CONDITIONS TA = 25C, f = 1MHz, Vcc = 5.0V
CCLK COUT
AC TEST LOADS AND WAVEFORMS
DATA RETENTION CHARACTERISTICS (-55oC < TC < 125oC; VCC = 5.0V +10%)
PARAMETER Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time 0.2V, Vcc = VDR = 2.0V, CE1\ > Vcc - 0.3V or CE2 < 0.3V, VIN > Vcc - 0.3V or VIN < 0.3V CONDITIONS SYM VDR ICCDR tCDR tR 0 200 MIN 2.0 150 MAX UNITS V A ns s
DATA RETENTION WAVEFORM
MT5C1008(LL) Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
MT5C1008(LL) Ultra Low Power
SWITCHING CHARACTERISTICS1 (-55oC < TC < 125oC; VCC = 5.0V +10%)
-30 PARAMETER SYM tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE 3 15 0 8 3 30 12 MIN 30 30 MAX UNITS ns ns ns ns ns ns ns ns ns 2, 3 3 2, 3 NOTES
READ CYCLE
Read Cycle Time Address to Data Valid Data Hold from Address Change CE1\ LOW to Data Valid, CE2 HIGH to Data Valid OE\ LOW to Data Valid OE\ LOW to Low Z OE\ HIGH to High Z CE1\ LOW to Low Z, CE2 HIGH to Low Z CE1\ HIGH to High Z, CE2 LOW to High Z
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WRITE CYCLE
Write Cycle Time CE1\ LOW to Write End, CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE\ Pulse Width Data Set-up to Write End Data Hold from Write End WE\ HIGH to Low Z WE\ LOW to High Z
tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE
30 22 22 0 0 22 18 0 5 8
ns ns ns ns ns ns ns ns ns ns
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3 2, 3
NOTES: 1. Test conditions assume signal transition time of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30pF load capacitance. 2. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5pF as in part (b) of AC Test Loads. Transition is measured 500mV from steady-state voltage. 3. At any given temperature and voltage condition, tHZCE < tLZCE, tHZOE < tLZOE, and tHZWE < tLZWE for any given device. 4. The internal write time of the memory is defined by the overlap of CE1\ LOW, CE2 HIGH, and WE\ LOW. CE1\ and WE\ must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. 5. The minimum write cycle time for Write Cycle No. 3 (WE\ controlled, OE\ LOW) is the sum of tHZWE and tSD.
MT5C1008(LL) Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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SRAM
Austin Semiconductor, Inc.
SWITCHING WAVEFORMS Read Cycle No. 11,2
MT5C1008(LL) Ultra Low Power
Read Cycle No. 2 (OE\ Controlled)2,3
NOTES: 1. Device is continuously selected. OE\, CE1\ = VIL, CE2 = VIH. 2. WE\ is HIGH for read cycle. 3. Address valid prior to or coincident with CE1\ transition LOW and CE2 transition HIGH.
MT5C1008(LL) Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
SRAM
Austin Semiconductor, Inc.
SWITCHING WAVEFORMS (continued) Write Cycle No. 1 (CE1\ or CE2 Controlled)1,2
MT5C1008(LL) Ultra Low Power
Write Cycle No. 2 (WE\ Controlled, OE\ HIGH During Write)1,2
NOTES: 1. Data I/O is high impedance if OE\ = VIH. 2. If CE1\ goes HIGH or CE2 goes LOW simultaneously with WE\ going HIGH, the output remains in a high-impedance state. 3. During this period the I/Os are in the output state and input signals should not be applied.
MT5C1008(LL) Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
SRAM
Austin Semiconductor, Inc.
SWITCHING WAVEFORMS (continued) Write Cycle No. 3 (WE\ Controlled, OE\ LOW)1
MT5C1008(LL) Ultra Low Power
NOTES: 1. If CE1\ goes HIGH or CE2 goes LOW simultaneously with WE\ going HIGH, the output remains in a high-impedance state. 2. During this period the I/Os are in the output state and input signals should not be applied.
MT5C1008(LL) Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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SRAM
Austin Semiconductor, Inc.
MT5C1008(LL) Ultra Low Power
MECHANICAL DEFINITIONS*
ASI Case #111 (Package Designator C)
S1
D
S2 A Q Pin 1 b b1 E L1 L
S
e
NOTE
0o to 15o
c E1
Detail A
ASI SPECIFICATIONS MIN MAX SYMBOL A --0.232 b 0.014 0.023 b1 0.038 0.065 c 0.008 0.015 D --1.700 E 0.350 0.405 E1 0.390 0.420 e 0.100 BSC L 0.125 0.200 L1 0.150 --Q 0.015 0.060 S --0.100 S1 0.005 --S2 0.005 --NOTE: Either configuration in detail A is allowed.
*All measurements are in inches.
MT5C1008(LL) Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
SRAM
Austin Semiconductor, Inc.
MT5C1008(LL) Ultra Low Power
ORDERING INFORMATION
EXAMPLE: MT5C1008C-30LL/MIL Device Package Speed Options** Process Number Type ns MT5C1008 C -30 LL /*
*AVAILABLE PROCESSES MIL = Military Processing (MIL-STD-883, para. 1.2.2 compliant) ** OPTIONS LL = 2V Data Retention/Ultra Low Power
-55oC to +125oC
NOTE: For other speeds and options, see the MT5C1008 data sheet (available from www.austinsemiconductor.com).
MT5C1008(LL) Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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